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| general description gd16555b is a 9.95328 gbit/s transmit - ter chip for use in sdh stm-64 and sonet oc-192 optical communication systems. gd16555b integrates all the main func - tions of the transmitter, which is clock generation, pll circuits and multiplexer in a single monolithic ic. hence only an external loop filter is required. the main functions of gd16555b are shown in the figure below. the clock generation is made on-chip by a low noise and tuneable 10 ghz vco. the vco centre frequency is controlled by a pll with an external loop filter, allowing the user to control the loop characteristic. the clock synchronisation is controlled by the phase and frequency detector with a 155 mhz or 622 mhz reference clock input (package bonding option). gd16555b multiplexes a 16 bit parallel 622 mbit/s interface into a serial 9.9553 gbit/s data stream. the output of the mux stage is retimed by the 10 ghz clock and the output driver is a current mode logic (cml) output with internal 50 termination re - sistors. the 16 bit wide parallel input interface is differential cml with 50 internal load termination, and with a 622 mhz clock output mastering the timing at the stm-4 interface. the phase of the output clock is selected in four phases: 0 ,90 , 180 , and 270 by two select pins. gd16555b is manufactured in a silicon bipolar process. gd16555b uses a single -5.2 v supply voltage. the power dissipation is 2 w, typical. gd16555b is delivered in a multi layer ceramic (mlc) package, with internal high-speed 50 transmission lines. an intel company data sheet rev.: 07 preliminary features on-chip low noise 10 ghz vco with a wide tuning range. automated capture of the vco frequency by a true phase and frequency detector. retiming of mux stage output with 10 ghz clock. clock failure detection nldet. 16:1 mux with differential 622 mbit/s cml data input. cml data input with 50 internal load termination. 622 mhz clock output for counter clocking. clock output is selectable in four phases: 0 ,90 , 180 ,or270 . 155 mhz or 622 mhz reference clock input (package bonding option). single supply operation: -5.2 v low power dissipation : 2 w (typ.). silicon bipolar process. 68 pin multi layer ceramic (mlc) package. applications telecommunication systems: ? sdh stm-64 ? sonet oc-192. fibre optic test equipment. submarime transmission systems. 10 gbit/s transmitter mux with re-timing gd16555b out tck vdd vddo vdda vee timing control vco 16:1 multiplexer phase frequency detector vctl s e l 3 (*) r e f c k r e f c k n sel2 sel1 din15 ff din0 di15 di0 ckout outn ckoutn nldet pclt (*) = package bonding option pout phigh plow vcur (only /155 vers.) parallel input data
functional details the main function of gd16555b is as transmitter in stm-64 and sonet oc-192 optical communication systems. it integrates: voltage controlled oscillator (vco) phase and frequency detector (pfd) 16:1 multiplexer re-timing of output data. vco the vco is an lc-type differential 10 ghz oscillator controlled by pin vctl and with a tuning range of 5%.the vco and the clock divider circuit gener - ates the clock signal and load pulses needed for multiplexing. it also generates the output clock (ckout/ ckoutn) and the clock used in the phase and fre - quency detector. with the vctl voltage at -3 v the vco frequency is fixed at 9.953 ghz and by changing the voltage from 0 to ? 5.2 v the frequency is controlled from 9 ghz to 10.2 ghz (see vco measurements on page 17 ). the modulation bandwidth of vctl is 90 mhz. pfd the pfd is made with digital set/reset cells giving it a true phase and frequency characteristic. the reference clock (refck/refckn) to the pfd is 155 or 622 mhz (package bonding option, two different product numbers). a no lock detection signal (nldet) is provided as a status signal of the pll. it compares the vco clock with the refer - ence clock and is high whenever they dif - fer. using nldet the situation of clock failure, i.e. loss of signal can be detected. the reference clock input has 50 inter - nal termination resistors to pin vcmlt and should be used differential. the pll will synchronize the 10 ghz vco to the external reference clock. noise from the reference clock, within the pll bandwidth will be multiplied and added to the 10 gbit/s output by the di - vider ratio between vco and reference clock i.e .n=16/64orin terms of noise as 20log(16) = 24 db or 36 db. a low noise reference clock with high frequency stability is required in order to fulfill the itu-t jitter requirements. inputs the parallel input interface is 622 mbit/s differential current mode logic (cml) with 50 internal resistors. the 16 bits are multiplexed starting with di0, di1...di15. all cml inputs have 50 internal termi - nation resistors to a separated power pin (vcmlt). with vcmlt connected to 0 v all inputs are configured as cml inputs (high/low equal 0/-0.4 v) or with vcmlt connected to ? 2 v all inputs are confi - gured as ecl compatible inputs (high/ low equal -0.8/ -1.8 v). with ecl inputs the maximum current out of vcmlt is 400 ma and proper de- coupling of vcmlt is required. the select inputs (sel1-2 and tck) are low-speed inputs, that can be connected directly to the supply rails (0 / -5.2 v). loop filter the external loop filter is made using an operational amplifier connected to output pins (phigh and plow). the character - istics of the phase lock loop are con - trolled by the loop filter components hence the op-amp is designed as an inte - grator by a feedback capacitor and a re- sistor. the gain-bandwidth of the op-amp need to be larger than the required pll bandwidth in order not to limit it. the rec- ommended op-amp is analog devices (ad8042) with a gain-bandwidth of 160 mhz sufficient for pll bandwidths up to 50 mhz. the op-amp is used single supplied by -5.2 v. see figure 1 for ap- plication information. the phase information from the pfd is high frequency pulses at output pins (phigh and plow). they are open col - lector outputs with an 8 ma current drive and are terminated externally by 220 to 0 v. a pre-filtering of the phase pulses are applied by a parallel 10 pf capacitor. the pcb layout of the external loop filter and the connecting lines to phigh, plow and vctl are critical for the jitter performance of the component. the art - work for the op-amp and the passive components should be placed very close to the pins of gd16555b in order to have connecting lines as short as possible. ideally the loop filter components are placed on the opposite side of the pcb directly underneath gd16555b. for more layout suggestions see the 10 gbit/s evaluation board gd90244/255. alternatively the phase information is also available at output pins (pctl and pout) and they can be used with an ex - ternal passive loop filter in applications with a low pll bandwidth (< 1 mhz) in - stead of the above recommended active loop filter. the pctl and pout pins should always be terminated as shown in figure 1 also even though they are not actively used in the pll. pout is a high impendance input and will be destroyed if connected directly (low-ohmic, <25 k )to-3.6vto0v. the outputs the output should be terminated exter - nally with 50 at the receive end and should be used differential. both out and outn are best terminated with the same load resistor e.g. 50 , an asym - metrically loading will decrease the per - formance of the output due to reflections. when terminated externally with 50 , the output voltage is 650 mv pp . both outputs out/outn are not esd protected and extra precautions should be taken when handling the outputs (the internal 50 resistor provides some esd hardness making the input low im - pedance). the clock outputs (ckout/n) are differ - ential open collector outputs wit ha8ma output current. they are terminated ex- ternally with a resistor (r) t o 0 v and the output voltage swing is v = -50 8 ma = -400 mv wit hr=50 . increasing the resistor increases the out- put voltage swing and reduces the band- width. counter clocking timing when the counter clocking timing is used to control the timing between gd16555b and the system asic, the output clock (ckout/ckoutn) is feed to the system asic and clocks valid output data from the asic into gd16555b. for easy inter - facing of the system asic, the output clock is selectable in four phases (0 , 90 , 180 or 270 ) by sel1-2. the maxi - mum variation in the round trip delay should be less than 1.1 ns when using the counter clocking timing. this leaves 0.5 ns of valid data time for the gd16555b . the roundtrip delay is the total delay from clock in, to data out of the system asic and the board delay for clock and data. the setup and hold times between ckout and input data are specified for all four phases (see ac characteristics on page 14 ). the valid time (e.g. the period of time where the in - put data is not allowed to change) is given by adding the setup and hold times. the setup time is defined positive before the rising edge of ckout. the hold time is defined positive after the ris - ing edge. data sheet rev.: 07 gd16555b page 2 of 20 if the variation is bigger than 1.1 ns an - other type of different clocking timing is needed e.g. forward clocking timing. it is recommended to use all data inputs differential for best performance. forward clocking timing with the forward clocking timing both the data and the clock is applied to gd16555b with the clock as a reference clock input (refck/refckn). see ac characteristics on page 15 . it is impor - tant for the jitter performance that the clock is clean with no spurious frequency noise and no noise injection from data transitions. if the clock is generated from a cmos asic an additional pll is needed to clean up the clock before be - ing applied as reference to gd16555b. when using gd16555b with forward clocking, the 622 mhz reference clock option should be ordered. the output voltage control for the gd16555b version with a 155 mhz reference clock (gd16555b/ 155-xx) a control signal (vcur) is avail - able at pin 41. by controlling the voltage at vcur the dc output voltage at out/outn is ad- justed in the range form 0.1 v to 0.8 v. the vcur can be operated fro m0vto vee. for the gd16555b version with a 622 mhz reference clock (gd16555b/ 622-xx) the control signal (vcur) is not available at pin 41. gd16555b versus gd16255a gd16555b is plug compatible and offers the same or even better performance compared with gd16255a. the pinouts and the configurations of i/o s are the same except of the three differences as described below: no reset pin sel 1/2 do not affect the timing rela - tion between the reference clock and the internal sampling of input data. the values of one resistor and capa - citor in the recommended loop filter. package gd16555b is packaged in a 68 pin multi layer ceramic package with internal 50 transmission lines. the package is a cavity-down type, which gives effective cooling using the mounted heat spreader. external circuits the main external circuits needed to make gd16555b work as a 10 gbit/s transmitter ic with re-timing and multi - plexer are: an active loop filter with op-amp a reference clock at 155 mhz or 622 mhz with high frequency stability pull up resistors and de-coupling ca - pacitors mounting and layout of pcb the component can be mounted on a standard fr4 epoxy printed circuit board when special attention is taken in the lay - out and in the mounting of the compo - nent. it is important for the performance of the component that the leads of pin out and outn (10 gbit/s outputs) are made very short (<1 mm) when mounted on the board. best way to make the leads short are to cut a hole in the pcb and to mount the component inside the hole. the length of the two critical leads is reduced to less than 0.5 mm whereas the rest of the leads are kept a t2-4mmin order for mechanical stability. on the back side the head spreader on the package is thermally mounted to a metal block with heat sink compound (see paragraph ? mounting of component on pcb ? on page 18 ). in cases where the above mounting tech - nical is not applicable, the component can be mounted directly on the board with bend leads accepting longer leads for the 10 gbit/s outputs. the component is available with straight leads and with gull wing leads (see the package outline drawings on page 19 ). in the layout of the pcb the 10 gbit/s in - puts are connected with 50 micro strip lines (msl) to the high- speed connec - tor. the msl should be as short as pos - sible (< 30 mm) with a plain and solid ground plan below. the layout artwork for the loop filter is placed preferable on the opposite side of the component with very short connections to the pins of gd16555b. the 100 resistors and 10 pf capacitor connected from phigh and plow t o 0 v should be placed very close to the package pin no. 50 and 53. the environment around the loop filter and the 10 gbit/s outputs is noise sensi - tive and no noise generating lines are allowed in this area. the power supply to gd16555b should be separated from other noise generation components on the board and de-cou - pled as shown on figure 2 . dc-dc con - verters are only allowed on the same board if proper noise filtering is applied. thermal condition the component dissipates 2.0 w with a ? 5.2 v voltage supply and need forced cooling with a heat sink thermally con - nected to the heat spreader. the thermal connection should ensure the case tem - perature in the range from 0 to 70 c with the given ambient conditions e.g. tempe - rature and air flow. power noise rejection in a noisy environment special attention must be taken as described above to op - timize the jitter performance and to re - duce the input sensitivity penalty from injected noise. the power supply rejec- tion ratio (psrr) is improved by adding a serial resistor (3.3 k ) and capacitor (33 nf) from the positive input of the op-amp to the power pin (vee) as shown in figure 1 . data sheet rev.: 07 gd16555b page 3 of 20 application figure 1. application information figure 2. de-coupling supply data sheet rev.: 07 gd16555b page 4 of 20 622 mbit/s cml driver 622 mbit/s cml driver 0v -5.2v 220 1k 1k ad8042 1k 1k 100 0.1 f 0.1 f 10pf 33nf 3.3k 0v 0v 0v 0v 100nf 3.3k + - 50 500 500 50 330 100nf vdd vdd -5.2v 0v tck/45 61 / di0 vcmlt 39 / di15 15 / ckout 62 / din0 40 / din15 16 / ckoutn 59 / nldet 47 / pctl 53 / plow 49 / pout 50 / phigh sel1 / 54 sel2 / 56 out/42 50 msl 50 msl 100nf 100nf 50 msl 0v 0v -5.2v 50 msl 50 msl 50 msl 0v 50 msl 50 msl 50 msl 50 msl vdd 10 gbit/s output outn / 44 refck / 57 reckn / 58 vctl / 46 vee 17/34/52 -5.2v vddo / 51 vdd 0v gd16555b 1 pin4 pin51 pin18 vdd vddo vcmlt vdda vee vee vee vee p ins 17/34/52 pin9 pin1 pin68 pin35 pin14 pin21 pin26 pin31 pin36 pin43 pin48 pin55 pin60 pin65 c cc c cc c cccccccccc 10f 10 f 10 f c is 10nf parallel with 100pf. 2 10 gbit/s output interface figure 3. 10 gbit/s outputs (out/outn), dc coupled figure 4. 10 gbit/s outputs (out/outn), ac coupled data sheet rev.: 07 gd16555b page 5 of 20 gd16555b driver 50 msl 50 50 0v -5.2v out outn gd16555b driver 50 msl 100nf 50 50 0v -5.2v out outn 622 mbit/s output interface figure 5. open collector output open collector outputs should always be terminated at the receiver end, preferably 50 . figure 6. ecl 100k or 10k output. ecl 100k or 10k output using ecl driver mc100el16/ mc10el16. figure 7. ecl compatible output ecl compatible output with a voltage swing of 600 mv (single-ended) or 1200 mv (differential). data sheet rev.: 07 gd16555b page 6 of 20 gd16544 or gd16555b 50 50 msl 8ma 0v -5.2v gd16544 or gd16555b 50 120 100nf 8ma (-1v) 0 v -5.2v -5.2v 0v ecl 100k/10k mc100el16 mc10el16 gd16544 or gd16555b 50 / 75 msl 95 365 8ma 0v -1.0v (high) -1.6v (low) -5.2v -5.2v figure 8. low voltage pecl output low voltage pecl output using pecl driver mc100lvel90/ mc10lvel90. figure 9. lvds compatible output reference clock input figure 10. reference clock input (refck/refckn), differential ac coupled. data sheet rev.: 07 gd16555b page 7 of 20 gd16544 or gd16555b 50 8ma -5.2v -5.2v +3.3v lvpecl 100k/10k mc100lvel90 mc10lvel90 120 100nf (-1v) 0 v gd16544 or gd16555b lvds input 50 msl 500 500 100 8ma +3.3v +3.3v +3.3v 0v -5.2v gd16555b 50 50 220 220 100nf refck refckn 0v 0v 0v -5.2v -5.2v -5.2v vcmlt 622 mbit/s input interface figure 11. cml input interface with a 0/-0.4 v input voltage swing (dc coupled) by connecting vcmlt to 0 v. figure 12. cml or lvds input interface with a 0/-0.4 v input voltage swing (ac coupled) by connecting vcmlt to 0 v. data sheet rev.: 07 gd16555b page 8 of 20 gd16555b 50 50 220 0v 0v 0v vcmlt cml or lvds output driver 100nf -5.2v -5.2v 50 msl gd16555b 50 50 msl 50 0v 0v 0v vcmlt cml driver -5.2v pin list mnemonic: pin no.: pin type: description: di0, din0 di1, din1 di2, din2 di3, din3 di4, din4 di5, din5 di6, din6 di7, din7 di8, din8 di9, din9 di10, din10 di11, din11 di12, din12 di13, din13 di14, din14 di15, din15 61, 62 63, 64 66, 67 2, 3 5, 6 7, 8 10, 11 12, 13 19, 20 22, 23 24, 25 27, 28 29, 30 32, 33 36, 37 39, 40 cml in data input, differential 622 mbit/s. multiplexed to serial output starting with di0, di1...di15. refck, refckn 57, 58 cml in reference clock input, differential 155 mhz or 622 mhz (package bonding option). sel1, sel2 54, 56 ecl in select the phase of ckout. sel1 sel2 00 t d =0 10 t d =90 01 t d =180 11 t d =270 out, outn 42, 44 cml out data output, differential 10 gbit/s. no internal esd output pro- tection . ckout, ckoutn 15, 16 open collector clock output, differential 622 mhz. should always be terminated with a resistor. pctl, pout 47, 49 analogue out/in phase-frequency detector outputs. phigh, plow 50, 53 open collector phase-frequency detector outputs. should always be terminated with 50 to vdd. vctl 46 analogue in vco input voltage control. nldet 59 open collector no lock detect output. should always be terminated with a re - sistor. tck 45 ecl in connect to vdd. used for test purpose. vddo 51 pwr vco ground 0 v. for test purpose connect to vee. vcmlt 18, 68 pwr cml input resistor termination voltage. vdd 4, 9, 14, 21, 26, 31, 38, 43, 48, 55, 60, 65 pwr digital ground 0 v. vdda 1, 35 pwr pll ground 0 v. vee 17, 34, 52 pwr -5.2 v digital supply voltage. vcur 41 analogue in output voltage control in gd16555b/155-xx versions. nc 41 connect to vee in gd16555b/622-xx versions. data sheet rev.: 07 gd16555b page 9 of 20 package pinout figure 13. package pinout, top view note: vdd = cavity data sheet rev.: 07 gd16555b page 10 of 20 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 vee ckoutn ckout vdd din7 di7 din6 di6 vdd din5 di5 din4 di4 vdd din3 di3 vdda vcmlt din2 di2 vdd din1 di1 din0 di0 vdd nldet refckn refck sel2 vdd sel1 plow vee vddo phigh pout vdd pctl vctl tck outn vdd out vcur/n c din15 di15 vdd din14 di14 vdda vee din13 di13 vdd din12 di12 din11 di11 vdd din10 di10 din9 di9 vdd din8 di8 vcmlt maximum ratings these are the limits beyond which the component may be damaged. all voltages in table are referred to vdd/vdda. all currents are defined positive out of the pin. vddis0vorgnd symbol: characteristic: conditions: min.: typ.: max.: unit: v ee negative supply 0 -6 v v cmlt cml resistor termination voltage 0 +0.7 v v o cml cml output voltage 0 v ee v i o cml cml output current note 1 0 -12 ma v i cml cml input voltage v cmlt -1.5 0.5 v i i cml cml input current note 1 -25 25 ma p out pout voltage v ee -3.6 v v esd static discharge voltage hbm, note 2 500 v cdm, note 3 50 v t j junction temperature -55 +125 o c t s storage temperature -65 +125 o c note 1: nominal supply voltages. note 2: human body model: mil 883d 3015.7 standard. note 3: charge device model.: jesd2-c101 standard. data sheet rev.: 07 gd16555b page 11 of 20 dc characteristics t case =0 cto70 c. all voltages in table are referred to vdd. all currents are defined positive out of pin. vddis0vorgnd symbol: characteristic: conditions : min.: typ.: max.: unit: v ee negative supply voltage -5.0 -5.2 -5.4 v v cmlt cml resistor termination voltage note 4 0 -2 v i ee supply current 330 400 480 ma v ih cml cml input voltage high, (50 input) v cmlt = 0v, note 3 -0.1 0 +0.1 v v il cml cml input voltage low, (50 input) v cmlt = 0v, note 3 -0.25 -0.4 -1.0 v v ih ecl ecl input voltage high, (50 input) v cmlt = -2v, note 3 -1.0 -0.8 -0.5 v v il ecl ecl input voltage low, (50 input) v cmlt = -2v, note 3 -1.6 -1.8 -2.0 v v oh oc open collector output voltage high note 1, 5 -0.05 0 +0.05 v v ol oc open collector output voltage low note 1, 5 -0.3 -0.4 -0.5 v i oh oc open output current high v cmlt = 0v, 50 input -0.1 0 +0.1 ma i ol oc open output current low v cmlt = 0v, 50 input -7 -8 -9 ma v oh out out/outn voltage high note 1, 10 mhz -0.1 -0.05 +0.05 v v ol out out/outn voltage low note 1, 10 mhz -0.6 -0.7 -0.8 v i oh out out/outn current high note 1 0 ma i ol out out/outn current low note 1 -14 ma v ih sel1-2, tck sel1-2 and tck input voltage high note 2 0 v ee +2 v v il sel1-2, tck sel1-2 and tck input voltage low note 2 v ee + 0.8 v ee v r in cml cml input resistor termination dc 45 50 55 note 1: output externally terminated by 50 to0v. note 2: sel1-2 and tck can be connected directly to vdd or vee. note 3: di0/din0 to di15/din15 are internally terminated by 50 to v cmlt . note 4: the cml inputs can be configured as ecl compatible by connecting v cmlt to -2 v, hence all data inputs and refck/ refckn have to be ecl. note 5: all open collector outputs should be terminated with a resistor to vdd even though they are not used. data sheet rev.: 07 gd16555b page 12 of 20 ac characteristics, general t case =0 cto70 c, vee = -5.2 v. symbol: characteristic: conditions: min.: typ.: max.: unit: j trf jitter transfer 12 kh z ac characteristics, forward clocking timing t case =0 cto70 c, vee = -5.2 v. figure 16. forward clocking timing. figure 17. timing relation between input data and reference clock. symbol: characteristic: conditions: min.: typ.: max.: unit: t s,rf di0-15 setup before refck vee = -5.2v, t c =70 , note 1, 2 100 ps t h,rf di0-15 hold from refck vee = -5.2v, t c =70 , note 1, 2 250 ps note 1: 622 mhz reference clock option. note 2: setup time is defined positive before the falling edge of ckout and the hold time is defined positive after the falling edge of ckout. data sheet rev.: 07 gd16555b page 15 of 20 16 bit @ 622 mbit/s differential reference clock 622 mhz di0 di15 refck refckn shift register pll asic system gd16555b t s,rf t h,rf refck di0-15 jitter transfer measurement figure 18. jitter transfer curve when connected with the recommended loop filter (see figure 1 ) on the evaluation board gd90244/255. the case temperature -5 cto85 c and power supply -5.0 v and -5.4 v. data sheet rev.: 07 gd16555b page 16 of 20 vco measurement figure 19. vco tuning curves. the tuning curves are measured at -5 c and 85 c and at supply voltages of -5 v and -5.4 v. data sheet rev.: 07 gd16555b page 17 of 20 mounting of component on pcb figure 20. example 1. mounting of the component inside a hole in the pcb with short leads for the 10 gbit/s inputs. the headspreader is down side to - wards the metal side for best cooling of the component. figure 21. example 2. mounting of the component on the pcb with bend leads (gullwings) the headspreader is thermal mounted to a heat sink. data sheet rev.: 07 gd16555b page 18 of 20 0.5 mm gd16555b 50 msl sma connector heat sink compound 2-4mm pcb metal block gd16555b 50 msl sma connector heat sink compound heat sink pcb loop filter package outline figure 22. package with straight leads figure 23. package with gullwings leads data sheet rev.: 07 gd16555b page 19 of 20 pin 1 0.750" +- 0.007" sq 0.950" +- 0.02" sq 17 18 34 35 51 52 68 0.010" 0.040" 0.056" +- 0.006" 0.086" +- 0.01" device marking figure 24. device marking, bottom and top view ordering information to order, please specify as shown below: product name: reference clock: package type: case temperature range: gd16555b/155-is 155 mhz 68 pin straight lead, multi layer ceramic, (mlc) 0...70 c gd16555b/622-is 622 mhz 68 pin straight lead, multi layer ceramic, (mlc) 0...70 c gd16555b/155-ig 155 mhz 68 pin gullwing lead, multi layer ceramic, (mlc) 0...70 c gd16555b/622-ig 622 mhz 68 pin gullwing lead, multi layer ceramic, (mlc) 0...70 c gd16555b, data sheet rev.: 07 - date: 2 november 2001 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.intel.com/ixa please check our internet web site for latest version of this data sheet. distributor: copyright ? 2001 giga aps an intel company all rights reserved an intel company gd16555b- |
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